The DeskPOD system gives you the flexibility and freedom of your own FPGA prototype board while providing the benefits of an integrated environment for simulation, FPGA prototype and software debugger

Traditional prototype boards are inflexible: You have to wait until the whole design is ready.

DeskPOD allows you to leverage the FPGA prototype earlier and easier.

As a result, you will have more schedule flexibility. You will have earlier access to the FPGA prototype: Hardware engineers will be able to accelerate simulation and software engineers will be able to test the target before the hardware is complete.

The key steps in the process are:

• RTL – gate equivalence checking
  • Use the RTL testbench to validate the FPGA synthesis
• Board validation
  • DeskPOD adaptor boards validated
  • Add your own daughter cards
• Prototype validation
  • Single FPGA board to validate each FPGA using the system test bench
  • Multi FPGA board to validate the whole system using the system test bench

These daughter cards allow you to add other components and build a connector to the final evaluation board that will allow you to verify the evaluation board. The main board supports up to two daughter cards so one can be for additional components and one for the "cable-in" connector.

If the additional daughter cards become too complex, it is always possible to customize the main adaptor board and include additional components on the main board itself.

The DeskPOD system enhances The SoC design and verification process that allows you to increase confidence in your design and save time and money.

Datasheet - DeskPOD Systems  [pdf]
 Describes the different DeskPOD systems and adaptor boards that are available. Ideal for somebody considering FPGA prototyping

Datasheet - Enhanced FPGA Prototyping  [pdf]
 Datasheet on how DeskPOD can be used to enhance FPGA prototyping

White paper - Enhanced FPGA Prototyping  [pdf]
 Overview of how the DeskPOD system enhances FPGA prototyping

DeskPOD FPGA system - data sheet    [pdf]
 Outlines the flow of creating the FPGA bitstream and linking it to simulation